1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device. In particular, the present invention relates to a method of accurately forming a micropattern using a pattern forming process using sidewall spacers.
2. Description of the Related Art
Advances in the scaling down of the pattern dimensions of semiconductor integrated circuits have accelerated remarkably. This accelerated scaling down depends on a photolithography technique, and this is expected to continue in future. The relationship between a pattern size (HP) expressed by half pitch and wavelength (λ) and lens numerical aperture (NA) used for an exposure (photolithography) system realizing it is expressed by the following Rayleigh equation.HP=k1*λ/NA 
If the pattern size is determined to meet market requirements (cost, device performance), the factor k1 included in the foregoing equation is a value showing the difficulty of lithography technique satisfying the requirements. (In this case, when the factor k1 is small, lithography is difficult.)
In general, the resolution limit of the pattern dimension using lithography is k1=0.25. If the factor k1 is less than 0.275, pattern forming using lithography becomes extremely difficult. According to the lithography in a range k1<0.275, two-beam coherence occurs. This depends on strong off-axis illumination. According to the strong off-axis illumination, lights passing through two points only on the outermost periphery of a pupil plane are imaged on a wafer. Illumination diagram generating the two-beam coherence is a so-called dipole. Under the condition of the strong off-axis illumination, a resolution performance of patterns other than the target minimum pattern pitch becomes extremely worse. For this reason, strong off-axis illumination such as dipole illumination is often used together with double exposure technique.
According to the double exposure, an LSI pattern is formed in the following manner. Specifically, patterns having the minimum pattern pitch are formed using the dipole illumination. Patterns other than the minimum pitch are formed using weak off-axis illumination such as annular illumination. The foregoing double exposure technique is readily applied to memory devices rather than logic devices. This is because the pattern random characteristic is strong in the logic devices. On the other hand, the minimum pattern pitch is limited to memory cell only in the memory devices. In this case, the memory cell is formed using strong off-axis illumination such as dipole illumination. Patterns other than the memory cell are formed using weak off-axis illumination technique such as annular illumination.
However, the scaling down of semiconductor devices requires a pattern dimension less than the foregoing factor, that is, k1<0.25. In a range of k1<0.25, the micropattern pitch more than the minimum pattern pitch formable using lithography is required. To give one example of the foregoing method, there has been known a pattern forming process using sidewall spacers (e.g., see U.S. Pat. No. 6,063,688). As shown in FIG. 1 to FIG. 8 of the foregoing USP Publication, a resist pattern is formed on a first film used as a dummy pattern after via a lithography process. Then, using the resist pattern as a mask, the first film is etched to form a dummy pattern, and thereafter, the resist is removed. A sidewall material, that is, second film is deposited on the dummy pattern. Thereafter, the second film is etched using RIE, and thereby, sidewall spacers are formed at the sidewalls of the dummy pattern. The dummy pattern is removed, and thereafter, a target film is etched using the sidewall spacers as a mask. In this case, a hard mask is selected as the target film, and then, the hard mask is slimmed (line width is reduced), and thereby, a finer micropattern is formable. Finally, the sidewall spacers are removed, and then, the process using sidewall spacers is completed. If the hard mask is used, the front-end film is etched, and thereafter, the hard mask is removed.
The following points are given as the features of the process using sidewall spacers.
1) The pitch of a pattern formed using lithography is twice as may the design pitch. In other words, pattern forming is possible using an exposure system before two or three generation.
2) The design pattern and the lithography target pattern (dummy pattern) are different.
3) Patterns having the same pattern size are formed on the entire surface.
4) Closed loop pattern is formed.
5) Dimensional accuracy is determined by the film thickness only of the sidewall spacer; therefore, dimensional controllability is high.
6) Line edge roughness is small.
Integrated circuit patterns are formed of various line width patterns in addition to the minimum line width. For this reason, the foregoing point 3) is given as a demerit to form a complicated integrated circuit pattern. Various proposals have been made as a process using the pattern forming process using sidewall spacers (e.g., see U.S. Pat. No. 6,475,891). According to process, a pattern size having the minimum line width is formed, and patterns having a size other than the minimum line width are formed.
However, according to these proposals, the following problem arises. Specifically, the patterns having the minimum line width and other patterns must be divided, and then, lithography is carried out using independent mask (so-called twice exposure process). For this reason, misalignment occurs between the minimum line width pattern and other patterns. Thus, a design must be made so that the misalignment does not influence devices. In order to achieve this, there is a need to secure a sufficient distance (alignment margin). The alignment margin intactly gives an influence to the chip size of device, and as a result, an unnecessarily large chip is given. Therefore, this process is carried out at high cost.
As described above, the pattern forming process using sidewall spacers has various advantages. On the other hand, patterns having the pattern size are formed on the entire surface. If patterns having various sizes are mixed and formed, exposure must be carried out every size. In this case, considering the misalignment, margin needs to be taken in a pattern design. This is a factor of make large the chip size. Moreover, if misalignment occurs in the pattern that the same transistors are repeatedly formed, the following problem arises. Specifically, unbalance occurs in characteristics between formed transistors. As a result, characteristic failure is a factor of reducing the yield.
Accordingly, it is desired to realize the following integrated circuit pattern forming method. According to the method, it is possible to prevent characteristic unbalance based on the misalignment and to prevent the chip area from being wastefully made large.